Projects

As the Moore’s Law states “The number of transistors per square inch on an IC doubles approximately every two years”

The advancement in Data Centre market especially on server side where a large amount of data needs to be transferred from one node to another node, requires a very high bandwidth communication medium. Such applications that require high data rates and bandwidths require a high-speed protocol capable of handling the transfers. Industry has come up with high-speed protocol called Peripheral Component Interconnect Express (PCIe).

PCIe is a high-speed serial computer expansion bus standard designed to replace the older PCI, PCI-X standards. PCIe can operate at a speed of 16GB/s/lane. PCIe has numerous improvements.

  1. Higher maximum system bus throughput
  2. Lower I/O pin count and smaller physical footprint
  3. Better performance scaling for bus devices
  4. More detailed error detection and reporting mechanism
  5. Native hot-plug functionality
PCIe1

A fabric is composed of point-to-point Links that interconnect a set of components – an example fabric topology.

The Switch

Switch is defined as a logical assembly of multiple virtual PCI-to-PCI Bridge devices. Switch is a complex device that acts as End point for Root Complex and as Root Complex for an Endpoint.

The Root Complex

A Root Complex (RC) denotes the root of an I/O hierarchy that connects the CPU/memory subsystem to the I/O.

The End Points

Endpoint refers to a type of Function that can be the Requester or Completer of a PCI Express transaction either on its own behalf or on behalf of a distinct non-PCI Express device (other than a PCI device or Host CPU)

PCIe-PCI/PCI-X Bridge

A PCI Express to PCI/PCI-X Bridge provides a connection between a PCI Express fabric and a PCI/PCI-X hierarchy.

PCIe Layering:

The PCIe is divided logically into three Layers

Transaction Layer

Data Link Laye

Physical Layer

diagram

Physical Layer

  • Logical Sublayer converts data received from the DLL to 8b/10b data or 128b/130b data based on the speed implemented.
  • Electrical Sublayer consists of drivers, input buffers, parallel–serial and serial – parallel conversion (SerDes), impedance matching

Data Link Layer

  • Link Management.
  • Error Correction.
  • TLP Sequencing.

Transaction Layer

  • Assembly and Disassembly of Transaction Layer Packets (TLP).
  • Event Management
  • Credit-Based flow control
Packet
Vlsi-Training

Course Description:

Understanding of PCIe system level
Know how PCIe Layer topology
Know how PHY Layer knowledge with hands-on coding
Know how DLL Knowledge with hands-on coding
Understanding of Transaction Layer

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Projects

8b/10b encoder, decoder implementation
LTSSM States modelling
PHY MAC Layer modelling/environment build
Data Link Layer Modelling/environment build
DLL and PHY layer integration

A few examples of endpoints are given below!

To add parallel processing power, GPU is attached to your host processor over PCIe.
asus
To connect your host processor to network of computers or interconnect, NIC (Network interface card) is attached over PCIe.
PCIe2 (1)
Secondary storage SSD (solid state drive) is attached to your processor over PCIe.
PCIe3
FPGA is attached to over PCIe to add configurable hardware or accelerators to your host processor
PCIe4
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